A conventional FeRAM has memory cells containing ferroelectric capacitors. Each ferroelectric capacitor contains a ferroelectric material sandwiched between conductive plates. To store data in a memory cell, a write operation applies write voltages to the plates of the ferroelectric capacitor to polarize the ferroelectric material in a direction associated with the data bit being written. A persistent polarization remains in the ferroelectric material after the write voltages are removed, which in turn maintains charge on the conductive plates.
A conventional read operation for a FeRAM cell connects one plate of a ferroelectric capacitor to a bit line and raises the other plate to a read voltage. If the persistent polarization in the ferroelectric capacitor is in a direction corresponding to the read voltage, the read voltage causes a relatively small current through the ferroelectric capacitor, resulting in a small voltage change on the bit line. If the persistent polarization initially opposes the read voltage, the read voltage flips the direction of the persistent polarization, discharging the plates and resulting in a relatively large current and voltage increase on the bit line. A sense amplifier can sense the stored value from the resulting bit line current or voltage.
FIG. 1A illustrates a portion of a conventional FeRAM 100 that includes memory cells 110 arranged in rows and columns to form a memory array. Only one column and two rows of memory cells 110 are shown in FIG. 1A for simplicity of illustration, but a typical FeRAM array may include hundreds or thousands of columns of memory cells with a similar number of rows. Each memory cell 110 of FeRAM 100 includes a ferroelectric capacitor 112 and a select transistor 114. Each select transistor 114 has a gate connected to a word line 116 corresponding to the row containing the memory cell and a source/drain connected to a bit line 120 corresponding to the column containing the memory cell.
A conventional read operation accessing a selected memory cell 110 in FeRAM 100 biases a plate of the selected memory cell to a plate voltage Vp (e.g., 3 V), and activates a selected word line 116 to turn on a select transistor 114 thereby electrically connecting the selected ferroelectric capacitor to bit line 120. The difference between the plate voltage and the initial bit line voltage forces the persistent polarization in the selected ferroelectric capacitor into a first state. Bit line 120 acquires a voltage that depends on the initial polarization state of the selected memory cell 110. In particular, if the selected memory cell was in a second state having a persistent polarization in a direction opposite to the persistent polarization of the first state, forcing the memory cell from the second state into the first state causes a relatively large current to bit line 120 and a corresponding rise in the bit line voltage. If the selected memory cell was already in the first state, a relatively small current flows to bit line 120.
A sense amplifier 130 connected to the bit line 120 compares the bit line voltage to a reference voltage Vref. A reference voltage generator (not shown) can generate reference voltage Vref at a level that is above the bit line voltage read out when the selected memory cell 110 has the first polarization state and below the bit line voltage read out when the selected memory cell 110 has the second polarization state. In sense amplifier 130, cross-coupled transistors drive bit line 120 to a logic level (high or low) depending on whether the bit line voltage was greater or less than reference voltage Vref. A bit thus read has a value indicated by the voltage on the bit line after operation of the sense amplifier.
FIG. 1B illustrates an alternative memory 100xe2x80x2 in which each memory cell 110xe2x80x2 includes two ferroelectric capacitors 112 and 112xe2x80x2 connected through respective select transistors 114 and 114xe2x80x2 to respective bit lines 120 and 120xe2x80x2. A write operation forces ferroelectric capacitor 112xe2x80x2 to a polarization state that is complimentary to the polarization state of ferroelectric capacitor 112. A read operation applies plate voltage Vp to both ferroelectric capacitors 112 and 112xe2x80x2 and activates a selected word line 116 to turn on select transistors 114 and 114xe2x80x2 and electrically connect selected ferroelectric capacitors 112 and 112xe2x80x2 to bit lines 120 and 120xe2x80x2, respectively. The read operation thus forces both ferroelectric capacitors 112 and 112xe2x80x2 to the first polarization state. The bit line 120 or 120xe2x80x2 connected to the ferroelectric capacitor 112 or 112xe2x80x2 initially in the second polarization state rises to a higher voltage. Sense amplifier 130 drives the bit lines 120 and 120xe2x80x2 connected to the memory cell initial in the second polarization state to complementary voltage, where the voltage on bit line 120 indicates the data bit read from the memory cell.
A read operation for FeRAM cell 110 or 110xe2x80x2 of FIG. 1A or 1B generally requires a write-back operation to restore a persistent polarization of a ferroelectric capacitor to the second state if the read operation forced the ferroelectric capacitor from the second state to the first state. In FeRAMs like 100 and 100xe2x80x2, sense amplifier 130 drives the bit lines 120 and 120xe2x80x2 to voltage suitable for the write-back operations. However, the driven voltage can interfere with uses of FeRAM that may require comparing a read-out bit line voltage to multiple different reference voltages. For example, an on-chip bit failure prediction, detection, and correction method might need to compare the read-out voltage from a memory cell to a series of reference voltages to determine whether the polarization state of the memory cell provides a bit line voltage large enough for an accurate read operation.
Using conventional read operations for comparisons to multiple reference voltages requires repeating the steps of reading a voltage out of a selected memory cell 110 to a bit line and sense amplifier, applying the first or next reference voltage to the sense amplifier, and comparing the read-out voltage to the applied reference voltage. Repetition of these operations is generally too slow for on-chip bit failure correction techniques. Additionally, write-back operations and time dependent failure mechanisms in ferroelectric materials make the charge delivered to a bit line or the voltage read out from a FeRAM cell vary from access to access, particularly because the polarization state of the FeRAM cell is refreshed between comparisons. The comparisons to different reference voltages thus may be inconsistent.
In view of the limitations to current read processes for FeRAM, improved processes and circuits for performing multiple comparisons are desired.
In accordance with an aspect of the invention, a read out voltage from a ferroelectric capacitor is compared to multiple reference voltages using a sense amplifier that does not disturb the read out voltage on a bit line. Accordingly, a fast series of comparisons can be performed to characterize the performance of an FeRAM cell, to anticipate or detect a bit error, or to read a multi-bit or multi-level value from a single ferroelectric capacitor.
The multiple-comparison operation includes reading out a voltage to a bit line that is otherwise floating and is coupled to a gate of a transistor in a sense amplifier. The read out voltage can be maintained while a series of reference voltages are applied to the sense amplifier for a series of sensing or comparison operations. When the series of operations is complete, a write-back operation restores the polarization state in the selected FeRAM cell.
One specific embodiment of the invention is a device including a bit line connected to FeRAM cells, a reference voltage generator capable of generating a series of voltage levels, and a sense amplifier connected to the bit line and the reference voltage generator. The sense amplifier, which can be a comparator-type sense amplifier, is capable of comparing the voltage on the bit line to each of the series of voltage levels without changing the voltage on the bit line. The device may further include an error detection circuit that predicts, detects, or corrects bit errors based on signals indicating results of comparing the voltage on the bit line to the series of voltage level. Alternatively, the FeRAM cell stores a multi-bit value, and the results of multiple comparisons of the voltage on the bit line to the series of voltage levels indicate the multi-bit value.
Another embodiment of the invention is a process including setting a voltage on a bit line according to a polarization state of an FeRAM cell and comparing the voltage on the bit line to each of multiple reference voltages, while keeping the voltage on the bit line constant throughout multiple comparisons. Applying a first voltage to a first plate of a ferroelectric capacitor in the FeRAM cell and connecting a second plate of the ferroelectric capacitor to the bit line while the bit line is floating can set the voltage on the bit line. The voltage on the bit line generally depends on an amount of current that flows through the ferroelectric capacitor. After completion of comparing the voltage on the bit line to each of the multiple reference voltages, writing back a data value read from the FeRAM cell can restore the polarization state of the FeRAM cell. Results from comparing the voltage on the bit line to each of the multiple reference voltages can characterize the operation of the FeRAM cell, indicate whether the FeRAM cell is operating properly, or indicate a multi-bit value stored in the FeRAM cell.
Yet another embodiment of the invention is a multiple-comparison operation including: (a) reading data out of a FeRAM cell to establish a bit line voltage on a first input node of a sense amplifier; (b) applying a first/next reference voltage to a second input node of the sense amplifier; (c) comparing the bit line voltage to the applied reference voltage, and (d) repeating steps (b) and (c) one or more times while keeping voltage on the first input of the sense amplifier constant.